1. Field of the Invention
The present invention relates to data sizing circuits in data flow type systems. More particularly, the present invention relates to a data sizing circuit in a data flow type system where a packet including an address signal, data, and a flag specifying read/write is passed in synchronism with a pulse signal so that data processing is carried out associated with the passing of the packet.
2. Description of the Related Art
FIG. 1 is a block diagram showing an example of a conventional data sizing circuit in a data flow type system. Referring to FIG. 1, a conventional data sizing circuit will be described. A data sizing circuit comprises transfer control circuits 201, 202, pipeline registers 203, 204, a memory 205, and an address decoder 206. A packet input line 212 is connected to pipeline register 203. A packet including data and address signals required for memory access and a read/write flag specifying the read/write is applied to packet input line 212, which is a parallel bit train propagated in synchronism with a pulse. The write data provided from pipeline register 203 is applied to memory 205 via data line 221. The read/write flag is applied to memory 205 via read/write flag line 222. A portion of the address signal provided from pipeline register 203 is directly applied to memory 205 via address line 223, as well as to address decoder 206 via address line 225. The output of address decoder 206 is applied to memory 205 via chip enable line 227 as a chip enable signal.
A portion of the packet which does not have its contents changed by memory access provided from pipeline register 203 is applied to a pipeline register 204 at a succeeding stage via packet transfer line 224. The data read out from memory 205 is applied to pipeline register 204 via read data line 226. A packet output line 214 is connected to the output of pipe line register 204.
A pulse input line 211 is connected to transfer control circuit 201. When a pulse signal is applied to pulse input line 211, transfer control circuit 201 applies a write pulse signal to pipeline register 203 immediately, and a pulse signal to transfer control circuit 202 after a predetermined time of delay. When a pulse signal is applied, transfer control circuit 202 supplies a write pulse signal to pipeline register 204 immediately, and a pulse signal to pulse output line 213 after a predetermined time of delay. Pipeline registers 203 and 204 fetch the data on the input line and hold the same while providing the same simultaneously, when a write pulse signal is applied.
When the read/write flag provided to read/write flag line 222 is set to a read value, and the chip enable signal provided from address decoder 206 is at an active state, memory 205 carries out reading operation to provide the data whose address is specified by the address signal applied from the address line 223 to read data line 226. When the read/write flag provided from read/write flag line 226 is set to a write value, and the chip enable signal provided from address decoder 206 is at an active state, memory 205 carries out writing operation to write the write data provided to write data line 221 to the address specified by the address signal provided from address line 223. The data provided to read data line 226 has the same value of the data in write data line 221, regardless of the state of the chip enable signal.
When the chip enable signal is not active, memory 205 attains a non-selected state, regardless of the signal state of other input lines, to hold the stored contents.
In accordance with the above described structure, the operation of reading from memory 205 is described hereinafter. A packet with a read value set in the read/write flag is applied to packet input line 212, and a pulse signal is applied to pulse input line 211. Transfer control circuit 201 applies a write pulse signal to pipeline register 203. Pipeline register 203 fetches and holds the packet provided from packet input line 212 in response to the write pulse signal. Then, transfer control circuit 201 provides a pulse signal to transfer control circuit 202 after a predetermined time. Meanwhile, the read/write flag provided from read/write flag line 222, the address signal applied from address line 223, and the write data applied from write data line 221 are available as the packet for memory 205 to carry out reading operation, to provide the data read out to read data line 226.
When a pulse signal is applied from transfer control circuit 201 to transfer control circuit 202, transfer control circuit 202 applies a write pulse signal to pipeline register 204. The data provided from read data line 226 and packet transfer line 224 are fetched and held in pipeline register 204, to be provided from packet output line 214. After a predetermined time, transfer control circuit 202 provides a pulse signal to pulse output line 213. Thus, a series of read processing is carried out. In the case of writing to memory 205, the read/write flag of the packet applied to packet input line 212 is set to a write value, whereby a writing process similar to the above mentioned serial read processing is carried out.
The conventional data sizing circuit of FIG. 1 has the following inconveniences. For the sake of explanation, it is presumed that data width is 32 bits, that is to say, each width of write data line 221 and read data line 226 is of a system of 32 bits. In this case, the read/write of the system is carried out at one time all in 32 bits width. Therefore, in write operation, data of 8 bits in width, for example, can not be used because the contents of the remaining 24 bits are destroyed at the time of writing data of 8 bits in width. Only the less significant 8 bits, for example, out of the 32 bits can be handled as being valid during processing of 8-bit wide data. That is to say, although 8 bits of data are valid and can be used even if the data region is 32 bits, the remaining 24 bits will be wasted entirely, to degrade the usage efficiency of memory 205.
The unit of the address in the system is automatically established to 32 bits. Assuming that the unit of the address is 8 bits in a 32-bit wide data, the location of a data whose address is 1 for example (8-bit unit) lies over two words of 32 bits in width, requiring access to two addresses. Therefore, handling will not be possible in the example of FIG. 1. In the case where such a processing of impossible handling is removed, the positioning of data will be limited to be carried out under a multiple of 4 when an address unit of 8 bits for example is to be used, because the address unit of word is 32 bits in the system.
When a write packet is applied to pipeline register 203 as the first packet, the above mentioned serial writing processing is carried out. When a pulse signal is provided from transfer control circuit 202 to pulse output line 213, the data sizing circuit returns to a waiting state. At this time, pipeline register 203 holds the contents of the first packet and continues to apply the data thereof to memory 205. In other words, the data sizing circuit is in a waiting state with a write flag applied from read/write flag line 222 to memory 205 and with a chip enable signal of an active state applied from chip enable line 227 to memory 205.
Under this state, a write packet with only the address signal provided to memory 205 via address line 223 differing from that of the first packet is applied as the second packet. Attention is directed to the change in the output data when the contents held in pipeline register 203 is updated to the contents of the second packet in response to the pulse signal applied from transfer control circuit 201. The read/write flag remains at a write value in this case. The chip enable signal also remains at an active state. In other words, when seen from the memory 205 side, the read/write flag and the chip enable signal remain stabilized in a write state and active state, respectively, with only the address signal changed. This provokes the problem of erroneous writing or destruction of the stored data, in view of the operational characteristic of memory 205 and whether all bits in address line 223 are actually altered simultaneously.
FIG. 2 shows the address signal applied to address line 223, the read/write flag provided from read/write flag line 222, and the chip enable signal provided from chip enable line 227. The above mentioned problems occur at time point t.sub.0 where only the address signal changes.